ASIC Verification Engineer

Profile

Description:
Create ASIC verification flows based on established guidelines
Duties will include:
Create test plans
Conduct test plan reviews with design team
Create and complete functional tests in a timely manner (constraint-random env)
Functional tests are to be easily reusable and ensure functional correctness of the ASIC designs
Interact with design and firmware teams to quickly debug test-case & corner-case test failures
Requirements:
Experienced verification experience using Verilog and System Verilog (OVM/UVM environments)
Experience in creating high coverage tests for complex ASIC’s
Python, perl, & TCL scripting languages
Ability to integrate components in test bench that were created in different languages (System Verilog, C, C )
Pluses
Storage and flash memory experience
Protocol knowledge experience like ( SAS, SATA, PCIE, USB, etc)
Education:
Bachelor's degree in Electrical or Computer Engineering; Master's degree preferred.
Minimum of 5 years experience.
Woody Arnold
Xpeerant Inc.
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